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Welcome

Welcome to the Poland Section Chapter, Solid-State Circuits Society website for the members of the IEEE. Here you will find important announcements, calendar of events, information on officers, other units, and useful links. Please use the navigation menu on top to browse the pages.

Poland has several universities and research institutes which are involved in the integrated circuits design activities. For the last few years we have also seen increasing number of small spin-off companies or branches of larger companies that deal with the design of integrated circuits. The idea of forming the SSCS Chapter was born after the visit of SSCS President, dr Rakesh Kumar in Poland in 2012. According to the decision of IEEE Member and Geographic Activities staff and IEEE Technical Activities staff on February 26, 2013, we are pleased to announce that Poland Section of Solid-State Circuit Society Chapter has been formed.

The SSCS Chapter Poland is focused on people from universities, research institutes and industry interested in integrated circuit design. The main tasks of IEEE SSCS Chapter Poland are:
- strengthen the relations between engineers and researchers from universities and industry working on solid state circuits,
- create and sustain enthusiasm for custom solid-state circuit design, especially among young engineers,
- increase the quality and innovation factor of our IC designs,
- learn about the latest developments in the field of integrated circuits,
- hold meetings, seminars, short courses for the members and invite distinguished lectures/researchers to Poland,
- keep close collaboration with Electron Device Chapter Poland.

Announcements

  • IEEE SSCS Chapter Poland together with TESPOL invites everyone for a seminar given by Tadeusz Asyngier (Tektronix Switzerland):
    "HI-SPEED INTERFACES: Methodology of measurement with Tektronix Instruments"
    - Measurements & observation of fast serial interfaces,
    - Characterization & analysis,
    - LVDS signalling, Jitter, BER, Eye-diagram, TIE,
    - Results interpretation
    - Hardware & accessories selection guide.
    Date & time: 11th June 2015, 11:15 - 14:00
    Lecture venue: AGH University of Science and Technology, bld. D-8, room: 402, Cracow, Poland.
    Agenda.

 

 
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Deployed: 20150406141335
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